Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) near text ";"; expecting a description`timescale 1ps/1ns;module mpeg2_ts_tb;reg clk,clkx2,rstn,sel,send ;reg [15:0] sample_ts[5120000 :0] ;reg [23:0] sample_cnt ;wire [15:0] data_16b ;wire [7
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Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) near text ";"; expecting a description`timescale 1ps/1ns;module mpeg2_ts_tb;reg clk,clkx2,rstn,sel,send ;reg [15:0] sample_ts[5120000 :0] ;reg [23:0] sample_cnt ;wire [15:0] data_16b ;wire [7
Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) near text ";"; expecting a description
`timescale 1ps/1ns;
module mpeg2_ts_tb;
reg clk,clkx2,rstn,sel,send ;
reg [15:0] sample_ts[5120000 :0] ;
reg [23:0] sample_cnt ;
wire [15:0] data_16b ;
wire [7:0] data_8b ;
initial
begin
$readmemh("../sample.dat",sample_ts);
end
initial
begin
clk = 1'b0 ;
clkx2 = 1'b0 ;
sel = 1'b0 ;
rstn = 1'b0 ;
send = 1'b0 ;
#1000 ;
rstn = 1'b1 ;
#1000;
send = 1'b1 ;
wait(sample_cnt == 5120000);
#1000;
$stop ;
end
always #20 clk = clk ;
always #10 clkx2 = clkx2 ;
always@(posedge clk or negedge rstn)
begin
if(!rstn)
begin
sample_cnt
Error (10170):Verilog HDL syntax error at mpeg2_ts_tb.v(1) near text ";"; expecting a description`timescale 1ps/1ns;module mpeg2_ts_tb;reg clk,clkx2,rstn,sel,send ;reg [15:0] sample_ts[5120000 :0] ;reg [23:0] sample_cnt ;wire [15:0] data_16b ;wire [7
1ps/1ns?1ps误差正负1ns?`timescale 1ns/100ps 正确写法,前面的是最小刻度,后面的是误差