请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEPTH = 0);SUBDESIGN altshift(data[(WIDTH - 1)..0] :INPUT;clock :INPUT = GND;aclr :INPUT = GND;clken :INPUT = VCC;result[(WIDTH - 1) ..0] :OUTPUT;)VARIABLEIF DEPTH > 0 GENERATEp

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请问如下程序是Verilog还是VHDL语言写的.PARAMETERS(WIDTH=4,DEPTH=0);SUBDESIGNaltshift(data[(WIDTH-1)..0]:INPUT;cloc

请问如下程序是Verilog 还是VHDL语言写的.PARAMETERS(WIDTH = 4,DEPTH = 0);SUBDESIGN altshift(data[(WIDTH - 1)..0] :INPUT;clock :INPUT = GND;aclr :INPUT = GND;clken :INPUT = VCC;result[(WIDTH - 1) ..0] :OUTPUT;)VARIABLEIF DEPTH > 0 GENERATEp
请问如下程序是Verilog 还是VHDL语言写的.
PARAMETERS
(
WIDTH = 4,
DEPTH = 0
);
SUBDESIGN altshift
(
data[(WIDTH - 1)..0] :INPUT;
clock :INPUT = GND;
aclr :INPUT = GND;
clken :INPUT = VCC;
result[(WIDTH - 1) ..0] :OUTPUT;
)
VARIABLE
IF DEPTH > 0 GENERATE
points[(DEPTH - 1)..0][(WIDTH - 1)..0] :DFFE;
END GENERATE;
BEGIN
IF DEPTH == 0 GENERATE
result[] = data[];
ELSE GENERATE
points[][].clk = clock;
points[][].clrn = aclr;
IF USED(clken) GENERATE
points[][].ena = clken;
END GENERATE;
points[0][].d = data[];
IF DEPTH > 1 GENERATE
FOR row IN 1 TO DEPTH - 1 GENERATE
points[row][].d = points[row - 1][].q;
END GENERATE;
END GENERATE;
result[] = points[DEPTH - 1][].q;
END GENERATE;
IF USED(result) GENERATE
result[] = GND;
END GENERATE;
END;