USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity suo_xian is port ( clk_out:in错误是：Else Clause following a Clock edge must hold the state of signal “ge2”

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USEieee.std_logic_1164.all;USEieee.std_logic_unsigned.all;entitysuo_xianisport(clk_out:in错误是：ElseCla

USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity suo_xian is port ( clk_out:in错误是：Else Clause following a Clock edge must hold the state of signal “ge2”
USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity suo_xian is port ( clk_out:in
错误是：Else Clause following a Clock edge must hold the state of signal “ge2”

USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; entity suo_xian is port ( clk_out:in错误是：Else Clause following a Clock edge must hold the state of signal “ge2”
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