gmsk的vhdl文件的解释library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity GMSK isport(clk:in std_logic;data:out std_logic;A3:out std_logic;A4:out std_logic;A5:out std_logic;A6:out std_logic;A7:out std_logic;A8:out std_

gmsk的vhdl文件的解释library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity GMSK isport(clk:in std_logic;data:out std_logic;A3:out std_logic;A4:out std_logic;A5:out std_logic;A6:out std_logic;A7:out std_logic;A8:out std_
gmsk的vhdl文件的解释
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity GMSK is
port(
clk:in std_logic;
data:out std_logic;
A3:out std_logic;
A4:out std_logic;
A5:out std_logic;
A6:out std_logic;
A7:out std_logic;
A8:out std_logic;
A9:out std_logic;
A10:out std_logic;
A11:out std_logic;
A12:out std_logic
);
end GMSK;
architecture address of GMSK is                --结构
signal count_4:integer range 0 to 1;
signal clk_2:std_logic;
signal clk_4:std_logic;
signal b1,b2,b3,b4,b5,b6:std_logic;
signal add_count:integer range 0 to 3;
signal m:std_logic_vector(6 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
    m<=(m(5 downto 0)&(m(4) xor m(0) xor(not(m(6)or m(5)or m(4)or m(3)or m(2)or m(1)or m(0)))));
    --生成m序列 k=7
    clk_2<=not clk_2;   --二分频
if(count_4=1) then  --四分频
    clk_4<=not clk_4; count_4<=0;
else
    count_4<=count_4+1; 
end if;
b1<=m(0);
b2<=b1;
b3<=b2;
b4<=b3;
b5<=b4;
b6<=b5;
if(b6='1') then
add_count<=add_count+1;
else
add_count<=add_count-1;
end if;
case add_count is           --象限数决定A6、A7
when 0=>A6<='0';A7<='0';
when 1=>A6<='1';A7<='0';
when 2=>A6<='0';A7<='1';
when 3=>A6<='1';A7<='1';
end case;
end if;
end process;
data<=b3;
A3<=clk_4;
A4<=clk_2;
A5<=clk;
A8<=b1;
A9<=b2;
A10<=b3;
A11<=b4;
A12<=b5;
end address;

图片是程序运行的结果图
这是一个GMSK调制的VHDL语言实现的代码    跪求大神指导各个句子的含义    在线等   急.
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gmsk的vhdl文件的解释library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity GMSK isport(clk:in std_logic;data:out std_logic;A3:out std_logic;A4:out std_logic;A5:out std_logic;A6:out std_logic;A7:out std_logic;A8:out std_
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; --库和程序包调用
entity GMSK is --实体定义,实体名GMSK
port --各个端口定义
(clk:in std_logic; --clk端口,in方向,标准逻辑位类型
data:out std_logic; --data端口,out方向,标准逻辑位类型
A3:out std_logic;
A4:out std_logic;
A5:out std_logic;
A6:out std_logic;
A7:out std_logic;
A8:out std_logic;
A9:out std_logic;
A10:out std_logic;
A11:out std_logic;
A12:out std_logic
);
end GMSK;
architecture address of GMSK is --结构体定义,结构体名address
--以下为结构体的用到的信号、数据类型等的声明
signal count_4:integer range 0 to 1; - -信号count_4定义,范围为0到1的整数
signal clk_2:std_logic; - -信号clk_2定义,标准逻辑位
signal clk_4:std_logic;
signal b1,b2,b3,b4,b5,b6:std_logic;
signal add_count:integer range 0 to 3;
signal m:std_logic_vector(6 downto 0); - -信号m定义,7位的标准逻辑位矢量
begin --结构体开始
process(clk) - -进程定义,敏感信号为clk
begin
if(clk'event and clk='1') then --如果clk事件发生并且clk=‘1’执行下述表达式
m