PROTEL 99 SE中,进行DRC检查出现如下错误是什么原因:Time :22:41:15Processing Rule :Clearance Constraint (Gap=5mil) (On the board ),(On the board )Rule Violations :0Processing Rule :Hole Size Constraint (Min=1mil) (Max=100mil) (On the boa

PROTEL 99 SE中,进行DRC检查出现如下错误是什么原因:Time :22:41:15Processing Rule :Clearance Constraint (Gap=5mil) (On the board ),(On the board )Rule Violations :0Processing Rule :Hole Size Constraint (Min=1mil) (Max=100mil) (On the boa
PROTEL 99 SE中,进行DRC检查出现如下错误是什么原因:
Time :22:41:15
Processing Rule :Clearance Constraint (Gap=5mil) (On the board ),(On the board )
Rule Violations :0
Processing Rule :Hole Size Constraint (Min=1mil) (Max=100mil) (On the board )
Rule Violations :0
Processing Rule :Width Constraint (Min=10mil) (Max=60mil) (Prefered=10mil) (On the board )
Rule Violations :0
Processing Rule :Broken-Net Constraint ( (On the board ) )
Violation Net RFVCC is broken into 2 sub-nets.Routed To 90.00%
Subnet :U7-3 C16-1 C13-1 U6-15 C14-1 U6-32 C17-2 U6-2 C15-1 U6-3
Subnet :U6-12
Violation Net GND1 is broken into 3 sub-nets.Routed To 85.71%
Subnet :DJ5-1 U8-4 C20-2 R27-2 J1-2 R13-1 R23-2 J1-1 C2-1 R24-1
R22-1 R21-1 U3-5
Subnet :R23-1
Subnet :R24-2
Rule Violations :2
Processing Rule :Short-Circuit Constraint (Allowed=Not Allowed) (On the board ),(On the board )
Rule Violations :0
Violations Detected :2
Time Elapsed :00:00:01

PROTEL 99 SE中,进行DRC检查出现如下错误是什么原因:Time :22:41:15Processing Rule :Clearance Constraint (Gap=5mil) (On the board ),(On the board )Rule Violations :0Processing Rule :Hole Size Constraint (Min=1mil) (Max=100mil) (On the boa
意思是"REVCC"与"GND1"这两个网络的线没连完全,你可以通过按“L”键,将所有的层设为不可见,仅飞线可见（如下图所示）,很容易就能看出未连接的飞线.