英语翻译4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:•\x05it has to be transmitted over a differential pair;•\x05for AC coupling it has to be DC free;•\x05it has to represent two st

英语翻译4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:•\x05it has to be transmitted over a differential pair;•\x05for AC coupling it has to be DC free;•\x05it has to represent two st
英语翻译
4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:
•\x05it has to be transmitted over a differential pair;
•\x05for AC coupling it has to be DC free;
•\x05it has to represent two states,receiver busy or ready.
We chose the flow control signal to be a square-wave because it is DC free and can easily be generated by clocked digital logic.The part of the FPGA which interfaces to the SerDes and performs the flow control is running at the same clock-speed as the parallel SerDes interfaces,e.g.125MHz for a 2.5Gbit/s link.The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency,i.e.62.5MHz.If the receiver is running out of FIFO space it signals the sender to stop by generating a square-wave at an eighth of the clock frequency.
These signals can be easily decoded by the sender FPGA even though they are not synchronous to any of the sender FPGA's clock signals.It does so by counting the number of clock cycles the flow control signal keeps the same value.If this counter is one to three the sender keeps sending,if it counts to four or more the sender has to stop.
We have to know at what receiver FIFO fill-level we have to signal a stop condition to the sender.It is the sum of the forward channel and the back channel latency.According to [16] the SerDes has a total link latency of 38 + 107 = 145 bit times,giving 7.25 clock cycles,plus the line delay of the cable.
The flow-control back channel has a latency equal to the line delay plus two cycles for the synchronizer registers,plus 4 to 5 cycles to detect the stop state.This adds up to 14.25 cycles plus two line delays.
At a 2m maximum cable length this is 2 x 2m / 0.5c = 26.6 ns which is 3.3 cycles.2 Thus the total delay should be less than 18 cycles.The latest time to dispatch the flow control stop signal is thus when we have 18 words of the 16bit receiver FIFO remaining free.
5) 32bit word synchronization:When using 32bit addresses,two 16bit words have to be transferred per address.In order to detect the 32bit word boundary we define that the two 16bit words have to be sent back-to-back,with no IDLE characters in between.Once an IDLE character is seen,the receiver knows the 32bit word boundary.This allows 32bit words to also be sent back-to-back,once the receiver has seen a single IDLE character,thus the full bandwidth available can be used for address data.
D.FPGA implementation
We are using a Xilinx Spartan 3E series FPGA on the AEX board to link the three interface sections together.The PQ208 package chosen has a sufficient pin count for this system,while still allowing in-house assembly without reflow soldering.

英语翻译4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:•\x05it has to be transmitted over a differential pair;•\x05for AC coupling it has to be DC free;•\x05it has to represent two st
4)\x05Flow-Control Scheme:The flow control signal has to fulfill the following requirements:
•\x05it has to be transmitted over a differential pair;
•\x05for AC coupling it has to be DC free;
•\x05it has to represent two states,receiver busy or ready.
We chose the flow control signal to be a square-wave because it is DC free and can easily be generated by clocked digital logic.The part of the FPGA which interfaces to the SerDes and performs the flow control is running at the same clock-speed as the parallel SerDes interfaces,e.g.125MHz for a 2.5Gbit/s link.The receiver FPGA signals that it is ready to receive by generating a square-wave at half its clock frequency,i.e.62.5MHz.If the receiver is running out of FIFO space it signals the sender to stop by generating a square-wave at an eighth of the clock frequency.
4.信息流控制方案：信息流控制信号必须符合下列要求：
* 信号必须通过一对差分线；
* 交流电的耦合必须没有直流；
* 它必须显示两种状态,接收器繁忙或准备接收.
我们选择的是方波信息流控制信号,因为它不需要直流且可以轻易由计时数字逻辑生成.与并串转换器连接和执行信息流控制的FPGA接口部件所运行的时钟速度是与并行接口一致的,例如2.5Gbit/s 的链接是125MHz.FPGA的接收器是以其时钟频率的一半生成方波信号表示已可接收信号,也就是62.5MHz.如果接收器已没有FIFO空间,它会用1/8的时钟频率生成方波信号通知发送器停止发信号.
These signals can be easily decoded by the sender FPGA even though they are not synchronous to any of the sender FPGA's clock signals.It does so by counting the number of clock cycles the flow control signal keeps the same value.If this counter is one to three the sender keeps sending,if it counts to four or more the sender has to stop.
We have to know at what receiver FIFO fill-level we have to signal a stop condition to the sender.It is the sum of the forward channel and the back channel latency.According to [16] the SerDes has a total link latency of 38 + 107 = 145 bit times,giving 7.25 clock cycles,plus the line delay of the cable.
尽管FPGA发送器没有与任何FPGA的时钟信号同步,但解码这些信号还是容易的.它是通过计算信息流控制信号维持同值的时钟周期数来实现的.如果周期数是一到三,发送器会继续发送信号,当达到四或以上时,发送器会停止发送.我们必须知道接收器的FIFO空间被装满至什么高度才应向发送器发送停止条件；这是前、后信道延时的总和.根据[16]中的串并转换器总共有链接时延38 + 107 = 145 位时间,有7.25个时钟周期,另加线缆的线路延时.
The flow-control back channel has a latency equal to the line delay plus two cycles for the synchronizer registers,plus 4 to 5 cycles to detect the stop state.This adds up to 14.25 cycles plus two line delays.
At a 2m maximum cable length this is 2 x 2m / 0.5c = 26.6 ns which is 3.3 cycles.Thus the total delay should be less than 18 cycles.The latest time to dispatch the flow control stop signal is thus when we have 18 words of the 16bit receiver FIFO remaining free.
信息流控制的后信道的时延是等于线路延时加同步注册器的2个周期,再加监测停止状态的四至五个周期,这合计达到14.25个周期加2个线路延时.
以最长2米的线缆计算,就是2 x 2m / 0.5c = 26.6 ns,即是3.3周期.因此,总延时应该低于18个周期.所以当16位接收器的FIFO空间只剩18字时,这是向信息流控制发送停止信号的最迟时间.
5) 32bit word synchronization:When using 32bit addresses,two 16bit words have to be transferred per address.In order to detect the 32bit word boundary we define that the two 16bit words have to be sent back-to-back,with no IDLE characters in between.Once an IDLE character is seen,the receiver knows the 32bit word boundary.This allows 32bit words to also be sent back-to-back,once the receiver has seen a single IDLE character,thus the full bandwidth available can be used for address data.
5.32位字同步：当使用32位地址时,每个地址必须转移两个16位字.为了检测32位字边界,我们的定义是,这两个16位字必须连续发送,中间不允许有IDLE字符.一旦有个IDLE字符被发现,接收器就知道32位字边界；这就让32位字也可以被连续发送,因此,全部的可用带宽能被用于地址数据.
D.FPGA implementation
We are using a Xilinx Spartan 3E series FPGA on the AEX board to link the three interface sections together.The PQ208 package chosen has a sufficient pin count for this system,while still allowing in-house assembly without reflow soldering.
D.运行FPGA
我们在AEX板上使用一个Xilinx Spartan 3E系列的FPGA将三个接口区连接起来.我们选择PQ208包是因为它有足够本系统使用的引脚数,而且不用再流焊就可进行内部组装.
【英语牛人团】

4）流量控制计划：流量控制信号，以满足下列要求：它必须通过一个差分对传输; 为交流耦合，它必须是直流自由; 它代表两个国家，繁忙或准备接收。我们选择的流量控制信号是一个方波，因为它是DC自由和主频数字逻辑可以很容易地产生。FPGA接口的SerDes和执行流量控制的一部分运行在并行SerDes接口，如为2.5Gbit / s的链路125MHz的时钟速度相同。接收器的FPGA信号，这是准备接收一半的时...

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4）流量控制计划：流量控制信号，以满足下列要求：它必须通过一个差分对传输; 为交流耦合，它必须是直流自由; 它代表两个国家，繁忙或准备接收。我们选择的流量控制信号是一个方波，因为它是DC自由和主频数字逻辑可以很容易地产生。FPGA接口的SerDes和执行流量控制的一部分运行在并行SerDes接口，如为2.5Gbit / s的链路125MHz的时钟速度相同。接收器的FPGA信号，这是准备接收一半的时钟频率产生一个方波，即中的62.5MHz。如果接收FIFO空间运行，它标志着发件人停止产生方波时钟频率的八分之一。这些信号可以很容易地由发件人的FPGA解码，即使它们是不同步的任何发件人FPGA的时钟信号。它是通过计数时钟周期数，流量控制信号保持相同的值。如果这个计数器是一至三年的发件人不断发送，如果数到4个或更多的发件人停止。我们要知道我们有什么接收器FIFO填充级发件人信号停止条件。这是前向通道和反向通道延迟的总和。据[16]的SerDes总链路延迟了38±107 = 145位的时间，使7.25个时钟周期，加上电缆线延迟。回通道的流量控制延迟等于行延迟加两个周期的同步寄存器，加上4至5次检测停止状态。这就增加了14.25个周期，加上两行延误。在2米的最大电缆长度是2×2米/ 0.5C = 26.6 ns的是3.3 cycles.2因此，总的延迟应小于18个周期。因此，当我们有18个字的16位接收FIFO中剩余的可用最新派遣流量控制停止信号的时间。5）32位字同步：当使用32位地址，两个16bit的话必须将每个地址传送。为了检测的32位字边界，我们定义了两个16位字之间没有空闲的人物，被发送到后端。一旦被视为空闲字符，接收方知道的32位字边界。这使得32位的话，也可以发送到后端，一旦接收已经看到了一个闲置的性格，因此可用带宽可以用地址数据。D. FPGA实现，我们正在使用AEX交易代号板赛灵思Spartan 3E系列FPGA连接三个接口部分。PQ208中包选择这个系统有足够的引脚数，同时还允许内部装配没有回流焊。

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流量控制的方案:在流量控制信号必须履行下列规定:
•必须鉴别对传送;
•AC耦合是直流自由;
有代表•这两个州,接收器忙或准备好了。
我们选择在流量控制信号是一个方波直流自由,因为它是和能容易地被以数字逻辑产生。这部分的SerDes FPGA接口,并进行流程控制运行在相同的clock-speed为平行SerDes接口、例句。125...

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流量控制的方案:在流量控制信号必须履行下列规定:
•必须鉴别对传送;
•AC耦合是直流自由;
有代表•这两个州,接收器忙或准备好了。
我们选择在流量控制信号是一个方波直流自由,因为它是和能容易地被以数字逻辑产生。这部分的SerDes FPGA接口,并进行流程控制运行在相同的clock-speed为平行SerDes接口、例句。125兆赫为2.5 Gbit / s链接。接收器FPGA的信号,它准备好去接受一个方波产生在时钟频率的一半,即。62.5赫兹。如果接收器快用光了先进先出法空间信号发送它停止产生一个方波在八分之一的时钟频率。
这些信号可以很容易地被解码的FPGA,即使他们发送不同步的FPGA的时钟信号的发送者。它这样做是通过计算时钟周期的数量在流量控制信号保持相同的数值。如果这个柜台一至三个发件人继续发送,如果有四个或更多的发件人必须停止。
我们必须知道我们必须接收信号fill-level FIFO停止条件对送礼的人。这是金额的通道和回了通道的延迟。根据[16]SerDes总共有潜在的联系+ 107 = 145点38次,给7.25时钟周期,加上线时延的电缆。
回来的流量控制通道有一个延迟等于线加两循环延迟同步器寄存器,加上4到5周期检测停止状态。这共计14.25周期加二线的延迟。
在一个2米的最高电缆长度这是2×2 m / 0.5 c = 26.6奈秒均为3.3的循环。2因此总延误应小于18周期。最新的时间调度流程控制停机信号是如此当我们有18个字的16位接收机FIFO剩余自由。
32位的字同步5):当使用32位的地址

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流量控制方案：流量控制信号以满足下列要求：
•已被传输一差动对的；
•交流耦合它是直流自由；
•它代表两国，接收器繁忙或准备。
我们选择的流量控制信号是方波直流自由，因为它是可以很容易地生成时钟数字逻辑。部分的接口到现场进行流量控制的运行在相同的时钟速度为并联机器人接口，例如，一个2.5gbit/s连接路。数字信号接收器，它已准备...

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流量控制方案：流量控制信号以满足下列要求：
•已被传输一差动对的；
•交流耦合它是直流自由；
•它代表两国，接收器繁忙或准备。
我们选择的流量控制信号是方波直流自由，因为它是可以很容易地生成时钟数字逻辑。部分的接口到现场进行流量控制的运行在相同的时钟速度为并联机器人接口，例如，一个2.5gbit/s连接路。数字信号接收器，它已准备好接收产生方波时钟频率的一半，即62.5mhz。如果接收器运行的先进先出空间信号发送停止产生方波在一个第八的时钟频率。
这些信号可以很容易地由发件人系统虽然不同步的任何发送器的时钟信号。它通过计数的时钟周期数，流量控制信号保持相同的值。如果该计数器是一个三发件人不断寄，如果罪名四个或多个发送者已停止。
我们已经知道什么接收机料位有一个停止条件发送信号。这是总结前向通道和后向通道延迟。根据[ 16]的串有一个总链接潜伏期为38 +107 =145位元时间，提供7.25个时钟周期，加上延时线的电缆。
流量控制后通道有一个延迟等于线延迟加双周期同步寄存器，加上4至5周期检测到停止状态。这增加了14.25个周期，加上2线延迟。
在200最大电缆长度是2×200/0.5℃=26.6纳秒是3.3个周期。2因此，总延迟要小于18周期。最新的时间调度流量控制停止信号，因此当我们有18字的16位接收机其余免费。
5）32位字同步：当使用32位地址，216位字已被转移，每个地址。为了检测32位字的边界定义我们的16位字已被发送到后端，没有空闲字符之间。一旦有空闲字符出现，接收器知道32位字边界。这使得32位字也被发送到后端，接收机一旦出现一个空闲字符，因此全带宽可用于地址数据。
D .实现
我们使用的是斯巴达人3系列产品板上连接三个接口部分在一起。pq208包的选择有足够的引脚数这一系统，同时仍然允许内部组件没有回流焊。

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