英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计

英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计
英语翻译
为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计的要求.图7,8是增益提高的频率特性,信号通路上的N型增益提升电路的负载电容为1pF,从图7中可以看出,其开环直流增益为24dB,单位增益带宽为1.44GHz,相位裕度为79°,P型增益提升电路的负载电容为0.6pF,从图8中的频率特性可以看出,其开环直流增益为28dB,单位增益带宽为1.39GHz,相位裕度为76°,满足设计要求.

英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计
为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.\x05
To test the circuit in the above paragraphs gain improve circuit and common-mode feedback circuit design is correct,the Chartered 0.18 um 1.8 V CMOS technology library,in Cadence software simulation environment circuit simulation.\x05
首先对2个增益提高进行了仿真,是否满足设计的要求.\x05
The first of two gain improve simulation,whether meet the design requirements.\x05
图7,8是增益提高的频率特性,信号通路上的N型增益提升电路的负载电容为1pF,从图7中可以看出,其开环直流增益为24dB,单位增益带宽为1.44GHz,相位裕度为79°,P型增益提升电路的负载电容为0.6pF,从图8中的频率特性可以看出,其开环直流增益为28dB,单位增益带宽为1.39GHz,相位裕度为76°,满足设计要求.\x05
Figure 7,8 is the gain improve frequency characteristics,signal path of ascension of n-type gain circuit load capacitance for 1 pF,can see from figure 7,the open loop dc gain for 24 dB,1.44 GHz bandwidth units gain,phase margin for 79 °,P type gain of the circuit for ascension load capacitance 0.6 pF,from the figure 8 can be seen in the frequency characteristics,the open loop dc gain for 28 dB,1.39 GHz bandwidth units gain,phase margin for 76 °,meet the design requirements.

In order to verify the above the circuit increases the gain circuit and common-mode feedback circuit design, using Chartered 0.18um 1.8V CMOS Technology Library, in the Cadence simulation environment ...

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In order to verify the above the circuit increases the gain circuit and common-mode feedback circuit design, using Chartered 0.18um 1.8V CMOS Technology Library, in the Cadence simulation environment for circuit simulation. The first of 2 increases the gain of simulation, can meet the design requirements. Figure 7, 8 is the gain increases the frequency characteristic, signal pathway on type N gain boost circuit load capacitance 1pF, as can be seen from Figure 7, the open loop DC gain of 24dB, unit gain bandwidth of 1.44GHz, and phase margin of 79 degree, type P gain boost circuit load capacitance for 0.6pF from figure 8, the frequency characteristics can be seen, the open loop DC gain of 28dB, unit gain bandwidth of 1.39GHz, and phase margin of 76 degree, to meet the design requirements.

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