Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(33) near text "elsif"; expecting "end",or "(",or

Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(33) near text "elsif"; expecting "end",or "(",or
Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"
Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"
Error (10500):VHDL syntax error at cqg.vhd(33) near text "elsif"; expecting "end",or "(",or an identifier ("elsif" is a reserved keyword),or a sequential statement
Error (10500):VHDL syntax error at cqg.vhd(35) near text "if"; expecting "case"
library ieee;
use ieee.std_logic_1164.all;
entity cqg is
port(clk,reset:in std_logic;
x:in std_logic_vector(1 downto 0);
sum_int:out std_logic_vector(3 downto 0);
sum_dec:out std_logic_vector(3 downto 0));
end cqg;
architecture behave of cqg is
type states is(s0,s1,s2);
signal current_state,next_state:states;
variable i1:std_logic_vector(3 downto 0);
variable d1:std_logic_vector(3 downto 0);
begin
reg:process(reset,clk)
begin
if clk'event and clk='1' then
if reset='1' then current_state

Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(31) near text ":="; expecting "then"Error (10500):VHDL syntax error at cqg.vhd(33) near text "elsif"; expecting "end",or "(",or

if d1:="1010" then d1:="0000";i1:=i1+"0001";应为if d1="1010" then d1:="0000";i1:=i1+"0001";

variable i1:std_logic_vector(3 downto 0);
variable d1:std_logic_vector(3 downto 0);

应当在引用变量的进程中变量声明,不能再结构体中声明普通变量,除非是共享变量（SHARED VARIABLE）.而且变量也不能作为敏感参量放在进程的敏感信号表当中.