请verilog的高手求助!帮帮新手写个程序!请用verilog,iplement a 32-bit ALU with the following function.ALU operation logic function00 A OR B01 A XOR B10 (A AND (B XNOR C))11 ((A XOR B) NAND C)the logic function should only be implement st
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请verilog的高手求助!帮帮新手写个程序!请用verilog,iplement a 32-bit ALU with the following function.ALU operation logic function00 A OR B01 A XOR B10 (A AND (B XNOR C))11 ((A XOR B) NAND C)the logic function should only be implement st
请verilog的高手求助!帮帮新手写个程序!
请用verilog,iplement a 32-bit ALU with the following function.
ALU operation logic function
00 A OR B
01 A XOR B
10 (A AND (B XNOR C))
11 ((A XOR B) NAND C)
the logic function should only be implement structurally using 2-input NAND,
2-input NOR & INVERTER GATES.the multiplexer should be implemented strucutally.
HINT:MAKE A 1-BIT ALU AND INSTANTIATE IT 32 TIMES
请verilog的高手求助!帮帮新手写个程序!请用verilog,iplement a 32-bit ALU with the following function.ALU operation logic function00 A OR B01 A XOR B10 (A AND (B XNOR C))11 ((A XOR B) NAND C)the logic function should only be implement st
module ALU(
sel,
a,
b,
c,
out);
input sel;
input [31:0] a,b,c;
output [31:0] out;
reg [31:0] out;
always @ (sel or a or b)
begin
case(sel)
2'b00:
begin
out = a | b;
end
2'b01:
begin
out = a ^ b;
end
2'b10:
begin
out = a & (~(b^c));
end
2'b11:
out = ~(a^b & c);
end
endmodule