xilinx FPGA 在调用ip核时,顶层模块调用后综合成功,但是implement时,map出问题总,怎么解决ERROR:Place:1206 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock source

xilinx FPGA 在调用ip核时,顶层模块调用后综合成功,但是implement时,map出问题总,怎么解决ERROR:Place:1206 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock source
xilinx FPGA 在调用ip核时,顶层模块调用后综合成功,但是implement时,map出问题总,怎么解决
ERROR:Place:1206 - This design contains a global buffer instance,
,driving the net,,that is driving the
following (first 30) non-clock source pins off chip.
< PIN:CLKOUT.O; >
This design practice,in Spartan-6,can lead to an unroutable situation due
to limitations in the global routing.If the design does route there may be
excessive delay or skew on this net.It is recommended to use a Clock
Forwarding technique to create a reliable and repeatable low skew solution:
instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to
Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to
.C1.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.Although the net
may still not route,you will be able to analyze the failure in FPGA_Editor.
< PIN "CLK75MhZ/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Place:1136 - This design contains a global buffer instance,
,driving the net,,that is driving the
following (first 30) non-clock source pins.
< PIN:CLKOUT.O; >
This is not a recommended design practice in Spartan-6 due to limitations in
the global routing that may cause excessive delay,skew or unroutable
situations.It is recommended to only use a BUFG resource to drive clock
loads.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
< PIN "CLK75MhZ/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; >
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

xilinx FPGA 在调用ip核时,顶层模块调用后综合成功,但是implement时,map出问题总,怎么解决ERROR:Place:1206 - This design contains a global buffer instance,,driving the net,,that is driving thefollowing (first 30) non-clock source
,driving the net,,that is driving the
following (first 30) non-clock source pins off chip.
CLK75MhZ/clkout1_buf是全局时钟布线,驱动一个向外输出的时钟引脚,因为该输出时钟引用啦全局时钟布线,故会选择芯片专用时钟输出引脚进行适配,如果这个被分配的引脚是普通IO就会造成适配失败.
可以把这个时钟改到专用时钟引脚,
也可以不用全局时钟走线.If you wish to override this recommendation,you may use the
CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote
this message to a WARNING and allow your design to continue.
在UCF文件中加入：NET "CLK75MhZ" CLOCK_DEDICATED_ROUTE = FALSE
不使用全局时钟布线.