英语翻译[1]Brajesh Kumar Kaushik∗,Sankar Sarkar,Rajendra P.Agarwal,and Ramesh C.Joshi,“Crosstalk noise generated byparasitic inductances in System-on-Chip VLSI interconnects”,HAIT Journal of Science and Engineering B,2007 ,Holon Institu

英语翻译[1]Brajesh Kumar Kaushik∗,Sankar Sarkar,Rajendra P.Agarwal,and Ramesh C.Joshi,“Crosstalk noise generated byparasitic inductances in System-on-Chip VLSI interconnects”,HAIT Journal of Science and Engineering B,2007 ,Holon Institu
英语翻译
[1]Brajesh Kumar Kaushik∗,Sankar Sarkar,Rajendra P.Agarwal,and Ramesh C.Joshi,“Crosstalk noise generated byparasitic inductances in System-on-Chip VLSI interconnects”,HAIT Journal of Science and Engineering B,2007 ,
Holon Institute of Technology.
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英语翻译[1]Brajesh Kumar Kaushik∗,Sankar Sarkar,Rajendra P.Agarwal,and Ramesh C.Joshi,“Crosstalk noise generated byparasitic inductances in System-on-Chip VLSI interconnects”,HAIT Journal of Science and Engineering B,2007 ,Holon Institu
[ 1]布拉杰库马尔考希克∗,sankar萨卡,拉金德拉页,和拉梅什·乔希,“串扰噪声的产生byparasitic片上互连电感”上,材料科学与工程学报,2007,全能技术研究所.[ 2]维尼塔deodhar,“throughput-centric波动流水线互连电路千兆集成”,论文.提出的学术教职：-电子及电脑工程学院乔治亚理工学院,十二月2005.[ 3] ] R顾和米埃尔马斯里,“功耗分析和优化的深亚微米数字电路,“美国固态电路学报,1996,31卷,5号,第707-713.[ 4]第王,克,和E看,“脉冲波互连,”杂志.超大规模集成电路系统,可以2004,12卷,5号,453页—463.[ 5]·张,诉乔治,和J .拉贝伊,“低摆幅片上信号技术：有效性和鲁棒性”,美国反.超大规模集成电路系统,六月2000,8卷,3号,264- 272页.[ 6]属忠和杰哈,“interconnect-aware高级合成低功率”,程序.国际参考计算机计算机辅助设计（年）,2002,pp110-117.[ 7]阿格涅斯卡ligocka-wardzinska沃伊切赫,bandurski,“敏感性分析的输出信号的超大规模集成电路的逆变器—interconnect-inverter系统参数选择”,阿格涅斯卡ligocka-wardzinska沃伊切赫,bandurski科技大学,波兹南,波兰,其技术回顾.[ 8]扬M拉贝伊,anantha切卓卡山,borivoje尼古莱´,“数字集成电路设计透视”,在电子和超大规模集成电路系列,2003.[ 9]拉扎维,“模拟集成电路设计”,麦格劳山的[ 10]康.美国米和莱布莱比西,“数字集成电路：分析与设计”,麦格劳山国际版本第三.[ 11]尼尔西部,戴维,“超大规模集成电路设计：电路和系统的观点》,第三版,艾迪生卫斯理.[ 12]尼尔的h.e.weste,eshraghian”原则,超大规模集成电路设计”,艾迪生卫斯理.分享到
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