object "process_en" on left-hand side of assignment must have a net type我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下module fifo_top(wr,data,clk,q,ready,process_en);input wr,clk;i
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object "process_en" on left-hand side of assignment must have a net type我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下module fifo_top(wr,data,clk,q,ready,process_en);input wr,clk;i
object "process_en" on left-hand side of assignment must have a net type
我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下
module fifo_top(wr,data,clk,q,ready,process_en);
input wr,clk;
input[7:0] data;
output ready,process_en;
output[7:0] q;
reg ready,process_en;
wire rd1,f1,e1,w1,co1;
assign rd1=ready;
assign process_en=~rd1;
assign w1=wr&process_en;
counter2 counter2(
.clk(clk),
.co(co1)
);
fifoo1 fifoo1(
.WE(w1),
.RE(rd1),
.WCLOCK(clk),
.RCLOCK(co),
.DATA(data),
.Q(q),
.FULL(f1),
.EMPTY(e1),
.AFULL(),
.AEMPTY()
);
df df(
.clr(e1),
.d(),
.clk(f1),
.q(rd1)
);
endmodule
object "process_en" on left-hand side of assignment must have a net type我用qusrturs 进行verilog语言编写一个顶层文件时候老是出现上面这个问题,具体程序段如下module fifo_top(wr,data,clk,q,ready,process_en);input wr,clk;i
简单 reg ready,process_en; 改为
reg ready；
wire process_en;