英语翻译Duty Cycle ControlWhen properly dimensioned,the four oscillator coreoutputs provide sinusoidal signals.According to therequirements for the signal waveform,the signals areeither directly applied to .the loads or drivers areconnected betwe

英语翻译Duty Cycle ControlWhen properly dimensioned,the four oscillator coreoutputs provide sinusoidal signals.According to therequirements for the signal waveform,the signals areeither directly applied to .the loads or drivers areconnected betwe
英语翻译
Duty Cycle Control
When properly dimensioned,the four oscillator core
outputs provide sinusoidal signals.According to the
requirements for the signal waveform,the signals are
either directly applied to .the loads or drivers are
connected between the oscillator and the load circuits.Inour prototype circuit,three-stage static CMOS inverter
chains (Fig.5) are added to provide a limiting function
and the driving capability for the 50 C2 measurement
equipment.The inverter chains convert the signal of the
core to a square wave signal (Fig.6).The duty cycle
requirement for this signal is usually 50 %.The comect
duty cycle is only ensured,if the core signal average
value U,(average of URF_~-U,,F.W,UW,and
URF_270.i)s equal to the switching threshold of the
drivers.As the average value depends on the imperfect
matching of the PMOS- and NMOS current sources,a
regulator circuit is added to provide broad-band duty
cycle control (Fig.7 right).The control current lFEQ is
converted to the control voltage Umos with a diode
connected transistor.The regulator circuit compares the
average output voltage U,with a reference voltage UREF
and adjusts UpMos to minimise the deviation between
U,and Uavs The voltage UREF can be derived from an
input-output shorted inverter (Fig 7 left) or from a
voltage divider.As the voltage divider for U,loads the
oscillator core,the oscillation vanishes for low oscillator
core current at about 100 MHz.Simulations indicate that
the minimum oscillation frequency can be as low as 1
MHz and the duty cycle is significantly enhanced,if the
voltage U,is derived from intermediate signals of the
drivers (Fig.5 b,c) instead of directly from the core
signals (Fig.5 a,realised in prototype circuit).

英语翻译Duty Cycle ControlWhen properly dimensioned,the four oscillator coreoutputs provide sinusoidal signals.According to therequirements for the signal waveform,the signals areeither directly applied to .the loads or drivers areconnected betwe
占空比控制
当适当的尺度,这四个振荡器核心
产出提供正弦信号.据
所需信号波形的信号
无论是直接适用.荷载或司机
连接之间的振荡器和负载电路. Inour原型电路,三个阶段的静态CMOS逆变
链（图5 ）被添加到提供一个限制功能
和驱动能力为50 C2测量
设备.链逆变转换的信号,
核心方波信号（图6 ） .的占空比
要求这个信号通常是50 ％ .该comect
占空比只有保证,如果核心信号平均
价值ü , , （平均URF_ 〜 - ü , ,化学家,威斯康星大学,和
URF_270.i ）秒等于开关阈值
司机.平均价值取决于不完善
匹配的PMOS -和NMOS电流源,一个
稳压电路被添加到提供宽带责任
周期控制（图7右） .控制是当前lFEQ
转换为控制电压Umos的二极管
连接晶体管.该稳压器电路比较
平均输出电压ü ,与参考电压系统联合
和调整,以尽量减少UpMos偏差
U和无人机的电压系统联合可以从一个
输入输出短路逆变器（图7左）或从
分压器.作为分压器的铀,加载
振荡器核心,振荡消失低振荡器
核心目前约为100兆赫.模拟表明,
最低振荡频率可低至1
频率和占空比显着提高,如果
电压ü , ,是来自中间信号
司机（图5乙,丙） ,而不是直接从核心
信号（图5 ,实现了原型电路） .