英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计

英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计
英语翻译
为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计的要求.图7,8是增益提高的频率特性,信号通路上的N型增益提升电路的负载电容为1pF,从图7中可以看出,其开环直流增益为24dB,单位增益带宽为1.44GHz,相位裕度为79°,P型增益提升电路的负载电容为0.6pF,从图8中的频率特性可以看出,其开环直流增益为28dB,单位增益带宽为1.39GHz,相位裕度为76°,满足设计要求.

英语翻译为验证上文对电路中增益提高电路和共模反馈电路设计的正确性,采用Chartered 0.18um 1.8V CMOS工艺库,在Cadence 软件仿真环境下进行电路仿真.首先对2个增益提高进行了仿真,是否满足设计
To verify the above circuit gain to improve correctness of common-mode feedback circuit and circuit design, using a Chartered 0.18um CMOS process, Cadence software for circuit simulation in the simulation environment. 2 gain first enhance the simulation, meets the design requirements. Figure 7,8 is gain improve of frequency characteristics, signal pathway Shang of n type gain upgrade circuit of load capacitance for 1pF, from Figure 7 in the can see, its open ring DC gain for 24dB, units gain bandwidth for 1.44GHz, phase margin for 79 °, p type gain upgrade circuit of load capacitance for 0.6pF, from Figure 8 in the of frequency characteristics can see, its open ring DC gain for 28dB, units gain bandwidth for 1.39GHz, phase margin for 76 °, meet design requirements.