什么是PLL
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什么是PLL
什么是PLL
什么是PLL
The MPLL within the clock generator,as a circuit,synchronizes an output signal with a reference input signal in
frequency and phase.In this application,it includes the following basic blocks as shown in Figure 7-2:the Voltage
Controlled Oscillator (VCO) to generate the output frequency proportional to input DC voltage,the divider P to
divide the input frequency (Fin) by p,the divider M to divide the VCO output frequency by m which is input to
Phase Frequency Detector (PFD),the divider S to divide the VCO output frequency by s which is Mpll (the output
frequency from MPLL block),the phase difference detector,the charge pump,and the loop filter.The output
clock frequency Mpll is related to the reference input clock frequency Fin by the following equation:
Mpll = (m * Fin) / (p * 2s)
m = M (the value for divider M)+ 8,p = P (the value for divider P) + 2
The UPLL within the clock generator is the same as the MPLL in every aspect.
The following sections describe the operation of the PLL,including the phase difference detector,the charge
pump,the Voltage controlled oscillator (VCO),and the loop filter.