VHDL编程求助：the following signal(s) form a combinatorial loop这是我的代码：目的是让数码管按照a>ab>b>bc>c>cd>d>de>e>ef>f>fa 循环发亮.library IEEE;use IEEE.STD_LOGIC_1164.ALL,IEEE.numeric_std.all;use IEEE.STD_LOGIC_ARITH.ALL;
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VHDL编程求助：the following signal(s) form a combinatorial loop这是我的代码：目的是让数码管按照a>ab>b>bc>c>cd>d>de>e>ef>f>fa 循环发亮.library IEEE;use IEEE.STD_LOGIC_1164.ALL,IEEE.numeric_std.all;use IEEE.STD_LOGIC_ARITH.ALL;
VHDL编程求助：the following signal(s) form a combinatorial loop
这是我的代码：目的是让数码管按照a>ab>b>bc>c>cd>d>de>e>ef>f>fa 循环发亮.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL,IEEE.numeric_std.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity first is
port( clk:in std_logic;
\x05\x05stop:in std_logic;
\x05\x05dout:out std_logic_vector(5 downto 0));\x05\x05
end first;
architecture Behavioral of first is
\x05constant clk_freq :integer := 50000000;
\x05constant scan_clk_freq :integer := 1000;
\x05constant clk_divisor :integer :=clk_freq/scan_clk_freq ;
\x05signal state:std_logic_vector(3 downto 0):="0001";
\x05signal scan_clk :std_logic;
\x05signal n1_clk :std_logic;
\x05signal n2_clk :std_logic;
\x05
\x05begin
\x05
\x05pro1 :process(clk) is
\x05variable count :natural range 0 to clk_divisor -1;
\x05 begin
\x05\x05if rising_edge(clk) then
\x05\x05\x05if count =clk_divisor - 1 then
\x05\x05\x05\x05count :=0;
\x05\x05\x05\x05scan_clk
VHDL编程求助：the following signal(s) form a combinatorial loop这是我的代码：目的是让数码管按照a>ab>b>bc>c>cd>d>de>e>ef>f>fa 循环发亮.library IEEE;use IEEE.STD_LOGIC_1164.ALL,IEEE.numeric_std.all;use IEEE.STD_LOGIC_ARITH.ALL;
提示那些信号是组合逻辑生成的,没有时钟驱动.
组合逻辑对点评敏感,这样写,问题很大.给pro3和pro4加上时钟.
其实你这pro3和pro4就是很明显的两端的状态机,好好看看书去吧.