英语翻译These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activi

英语翻译These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activi
英语翻译
These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activity).The source addressevents (AEs) being transmitted on the digital bus can be translated,converted or remapped to multiple destinations using conventional logic and memory elements.AER infrastructures therefore allow us to construct large multi-chip networks with arbitrary connectivity,and to seamlessly reconfigure the network topology.
As the trend to develop complex AER multi-chip experimental setups is increasing,there is a strong need for robust and reliable AER communication infrastructures,that can be easily interfaced to workstations or laptops during a prototyping phase,and that can be embedded into compact and low-cost systems in the application phase.
Existing AER Infrastructure and Approaches
Conventional approaches that use general purpose hardware in multi-chip AER systems involve logic-analyzers or general purpose digital data acquisition systems,but these approaches usually suffer drawbacks regarding asynchronous communication or on-line analysis of the acquired data [3].This requires the design of special purpose hardware for building and debugging multi-chip AER systems.
For example a generic AER interfacing solution implemented using special purpose hardware is the PCI-AER board [3].It consists of a custom made PCI card and a daughter board which are connected by a ribbon cable.The daughter board has parallel AER interface connectors and supports up to four input channels and four output channels.The PCI board consists of multiple FPGAs,FIFOs,SRAM and a PCI interface controller chip.The PCI board can monitor 备注0 incoming AE streams and then send the timestamped AEs via PCI to a program running on the computer.It can also do the reverse:sequence 备注0 timestamped data provided to it over the PCI bus out on any or all of the output channels.The FPGAs on the PCI-AER board also implement a one to many mapper that can be reconfigured via the PCI interface.
Recent boards for interfacing AER to PC were also implemented using USB instead of PCI,e.g.[10].
Similarly,recent serial AER communication schemes were proposed in [11].
Other groups building multi-chip AER systems tend not to use generic AER infrastructure,but build special purpose PCBs on a perproject basis e.g.[2],[12],or analogous solutions that are not as flexible,or powerful,as the system described here.
Here we propose a general purpose serial AER infrastructure that can be reused in multiple projects or experimental setups.

英语翻译These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activi
These multiplexing strategies are very efficient because only the addresses of active elements are transmitted (as opposed to conventional scanning techniques that allocate the same bandwidth for all the pixels,independent of their activity).The source address events (AEs) being transmitted on the digital bus can be translated,converted or remapped to multiple destinations using conventional logic and memory elements.AER infrastructures therefore allow us to construct large multi-chip networks with arbitrary connectivity,and to seamlessly reconfigure the network topology.
As the trend to develop complex AER multi-chip experimental setups is increasing,there is a strong need for robust and reliable AER communication infrastructures,that can be easily interfaced to workstations or laptops during a prototyping phase,and that can be embedded into compact and low-cost systems in the application phase.
由于只传输有源元件的地址,这些多路复用策略的效率很高（相对于只分配相同带宽予所有像素,而不受它们活动影响的常规扫描技术而言）.通过利用常规逻辑和储存元件,可以将
在数字总线上传输的AEs源翻译、转换或映射到多个目标.因此,AER基础结构可以让我们建立能任意连接的大型多芯片网络,以及无缝地重新配置网络拓扑.
鉴于综合AER多芯片实验设备的发展趋势日益增强,极力需要一种坚实耐用和可靠的通信基础设备,在其原型开发期间易于连接至工作站或者笔记本电脑,而且在使用期可以嵌入到小巧和低价的系统.
Existing AER Infrastructure and Approaches
Conventional approaches that use general purpose hardware in multi-chip AER systems involve logic-analyzers or general purpose digital data acquisition systems,but these approaches usually suffer drawbacks regarding asynchronous communication or on-line analysis of the acquired data [3].This requires the design of special purpose hardware for building and debugging multi-chip AER systems.
现行的AER基础设备和方法
在多芯片AER系统中使用一般用途硬件的常规方法会涉及使用逻辑分析仪或者一般用途的数字数据采集系统,但这些方法在异步通信方面或对采集的数据进行分析时通常会遭遇问题[3].这需要设计一个专用硬件来建立和调试多芯片AER系统.
For example a generic AER interfacing solution implemented using special purpose hardware is the PCI-AER board [3].It consists of a custom made PCI card and a daughter board which are connected by a ribbon cable.The daughter board has parallel AER interface connectors and supports up to four input channels and four output channels.The PCI board consists of multiple FPGAs,FIFOs,SRAM and a PCI interface controller chip.The PCI board can monitor incoming AE streams and then send the time stamped AEs via PCI to a program running on the computer.It can also do the reverse:sequence timestamped data provided to it over the PCI bus out on any or all of the output channels.The FPGAs on the PCI-AER board also implement a one to many mapper that can be reconfigured via the PCI interface.
例如,利用专用硬件执行一个普通的AER接口解决方案的是PCI-AER 主板[3].它含有一张定制的PCI卡和一张以排线连接的子板.子板上有并行的AER接口连接器,可以支持四个输入和四个输出通道.PCI主板上拥有多个FPGAs、FIFOs、SRAM 以及一个PCI接口控制器芯片.这PCI主板能够监控传入的AE信息流,然后将已时间戳的AE通过PCI传至正在计算机中运行的程序.它也可以反过来操作,将接收到有时间戳的数据顺序通过PCI总线传至任何或所有的输出通道.在PCI-AER主板上的FPGA也可执行从单一至许多通过PCI接口重新配置的映射器.
Recent boards for interfacing AER to PC were also implemented using USB instead of PCI,e.g.[10].Similarly,recent serial AER communication schemes were proposed in [11].Other groups building multi-chip AER systems tend not to use generic AER infrastructure,but build special purpose PCBs on a per project basis e.g.[2],[12],or analogous solutions that are not as flexible,or powerful,as the system described here.
Here we propose a general purpose serial AER infrastructure that can be reused in multiple projects or experimental setups.
AER接口连接个人电脑的主板最近也执行使用USB而不用PCI,如[10]..同样的,连续的AER通信方案最近也被提议在[11].其他构建多芯片AER系统的组织,趋向于按每个项目建立专用PCB,而不使用普通的AER基础设备.例子[2],[12]；或者使用在灵活性或大功率方面都比这里所阐述的系统较逊色的类似解决方案.
我们在这推荐一般用途的连续AER基础设备,它可以在多个项目或实验设备中重复使用.
【英语牛人团】

这些复用策略是非常有效率,因为只有的地址传送活性成分(与常规扫描技术能分配到相同的带宽的像素,独立的运动)。addressevents(AEs)的来源被传输数字化公共汽车能被转化,转化为多个目的地或remapped使用传统的逻辑与记忆的元素。因此让我们大量基础设施建设大型网络连通性multi-chip武断,无缝重配置网络拓扑结构。
发展趋势multi-chip实验设置复杂的大量增加,有一种...

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这些复用策略是非常有效率,因为只有的地址传送活性成分(与常规扫描技术能分配到相同的带宽的像素,独立的运动)。addressevents(AEs)的来源被传输数字化公共汽车能被转化,转化为多个目的地或remapped使用传统的逻辑与记忆的元素。因此让我们大量基础设施建设大型网络连通性multi-chip武断,无缝重配置网络拓扑结构。
发展趋势multi-chip实验设置复杂的大量增加,有一种强烈的需要大量耐用和可靠的通信基础设施,可以很容易地用于笔记本电脑工作站或在原型阶段,并能在嵌入式小型、低成本的系统在应用阶段。
现有大量基础设施和方法
传统的方法使用通用硬件系统都logic-analyzers正在multi-chip或通用数字的数据采集系统,但这些方法通常是苦的缺陷有关异步通讯或在线分析获取的数据[3]。这就要求设计特殊目的的硬件建设和调试multi-chip正在系统。
例如一个通用的接口方案正在实施的目的是用特殊的硬件PCI-AER板[3]。它由一个定制了PCI卡和一个女儿板是由一个带连接电缆。女儿,你正在接口板具有平行连接器和支持多达四个输入通道和四个输出通道。一种总线标准板由多种fpga,FIFOs,静态存储器和一个一种总线标准接口控制器芯片。一种总线标准博

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