在verilog里always和 initial的区别是什么?module tb_fulladder;wire SUM,C_OUT;reg A,B,C_IN;fulladder m1(.sum(SUM),.c_out(C_OUT),.a(A),.b(B),.c_in(C_IN));initialbeginA=1'd0;B=1'd0;C_IN=1'd0;#5 A=1'd1;B=1'd1;C_IN=1'd1;#5 A=1'd0;B=1'd1;C_IN=1'd1;#

在verilog里always和 initial的区别是什么?module tb_fulladder;wire SUM,C_OUT;reg A,B,C_IN;fulladder m1(.sum(SUM),.c_out(C_OUT),.a(A),.b(B),.c_in(C_IN));initialbeginA=1'd0;B=1'd0;C_IN=1'd0;#5 A=1'd1;B=1'd1;C_IN=1'd1;#5 A=1'd0;B=1'd1;C_IN=1'd1;#
在verilog里always和 initial的区别是什么?
module tb_fulladder;
wire SUM,C_OUT;
reg A,B,C_IN;
fulladder m1(.sum(SUM),
.c_out(C_OUT),
.a(A),
.b(B),
.c_in(C_IN));
initial
begin
A=1'd0;B=1'd0;C_IN=1'd0;
#5 A=1'd1;B=1'd1;C_IN=1'd1;
#5 A=1'd0;B=1'd1;C_IN=1'd1;
#5 A=1'd1;B=1'd0;C_IN=1'd0;
#5 A=1'd1;B=1'd1;C_IN=1'd0;
end
endmodule
这为什么用 initial

在verilog里always和 initial的区别是什么?module tb_fulladder;wire SUM,C_OUT;reg A,B,C_IN;fulladder m1(.sum(SUM),.c_out(C_OUT),.a(A),.b(B),.c_in(C_IN));initialbeginA=1'd0;B=1'd0;C_IN=1'd0;#5 A=1'd1;B=1'd1;C_IN=1'd1;#5 A=1'd0;B=1'd1;C_IN=1'd1;#
initial块内的语句从上到下只执行一次 不符合电路的运行模式 所以是不可综合的 它一般用来仿真时赋值；你这个代码里面的initial就是用来给输入赋值测试你这个全加器的.
always块内的语句是反复执行的 一般写成类似于 always @ (posedge clock or negedge reset) 或 always @ (*)的形式写成时序或组合逻辑