EI检索号查询谁可以告诉我怎么查询一篇文章的EI检索号?文章名字：A Novel Analytical Thermal Model for Multilevel Nano-scale Interconnects Considering Via Effect这篇文章好像SCI和EI都收录了,请大家帮我查一下检

EI检索号查询谁可以告诉我怎么查询一篇文章的EI检索号?文章名字：A Novel Analytical Thermal Model for Multilevel Nano-scale Interconnects Considering Via Effect这篇文章好像SCI和EI都收录了,请大家帮我查一下检
EI检索号查询
谁可以告诉我怎么查询一篇文章的EI检索号?
文章名字：A Novel Analytical Thermal Model for Multilevel Nano-scale Interconnects Considering Via Effect
这篇文章好像SCI和EI都收录了,请大家帮我查一下检索号,

EI检索号查询谁可以告诉我怎么查询一篇文章的EI检索号?文章名字：A Novel Analytical Thermal Model for Multilevel Nano-scale Interconnects Considering Via Effect这篇文章好像SCI和EI都收录了,请大家帮我查一下检
恭喜,EI有两个版本：
1. Accession number: 10967689

Title: A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Authors: Zhu Zhang-Ming1 ; Li Ru1 ; Hao Bao-Tian1 ; Yang Yin-Tang1

Author affiliation: 1 Microelectron. Inst., Xidian Univ., Xi'an, China


Source title: Chinese Physics B

Abbreviated source title: Chin. Phys. B (UK)

Volume: 18

Issue: 11

Publication date: Nov. 2009

Pages: 4995-5000

Language: English

ISSN: 1674-1056

Document type: Journal article (JA)

Publisher: IOP Publishing Ltd.

Country of publication: UK

Material Identity Number: GB54-2009-013

Abstract: Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (PCMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies.

Number of references: 13

Inspec controlled terms: CMOS integrated circuits - current density - diffusion - integrated circuit interconnections - semiconductor device models - thermal conductivity

Uncontrolled terms: analytical thermal model - multilevel nanoscale interconnects - heat diffusion equation - complementary metal oxide semiconductor process parameter - CMOS process parameter - thermal conductivity reduction - current density - computer aided design - CAD - very large-scale integrated circuits - nanoscale technology

Inspec classification codes: B2570D CMOS integrated circuits - B2550N Nanometre-scale semiconductor fabrication technology - B2560B Semiconductor device modelling and equivalent circuits - B2550F Metallisation and interconnection technology

Treatment: Practical (PRA); Theoretical or Mathematical (THR)

Discipline: Electrical/Electronic engineering (B)

DOI: 10.1088/1674-1056/18/11/063

Database: Inspec
2. Accession number: 20094812503554

Title: A novel analytical thermal model for multilevel nano-scale interconnects considering the via effect

Authors: Zhu, Zhang-Ming1 ; Li, Ru1 ; Hao, Bao-Tian1 ; Yang, Yin-Tang1

Author affiliation: 1 Microelectronics Institute, Xidian University, Xi'an 710071, China


Corresponding author: Zhu, Z.-M. ([email protected])

Source title: Chinese Physics B

Abbreviated source title: Chin. Phys.

Volume: 18

Issue: 11

Issue date: 2009

Publication year: 2009

Pages: 4995-5000

Language: English

ISSN: 16741056

Document type: Journal article (JA)

Publisher: Institute of Physics Publishing, Temple Back, Bristol, BS1 6BE, United Kingdom

Abstract: Based on the heat diffusion equation of multilevel interconnects, a novel analytical thermal model for multilevel nano-scale interconnects considering the via effect is presented, which can compute quickly the temperature of multilevel interconnects, with substrate temperature given. Based on the proposed model and the 65 nm complementary metal oxide semiconductor (CMOS) process parameter, the temperature of nano-scale interconnects is computed. The computed results show that the via effect has a great effect on local interconnects, but the reduction of thermal conductivity has little effect on local interconnects. With the reduction of thermal conductivity or the increase of current density, however, the temperature of global interconnects rises greatly, which can result in a great deterioration in their performance. The proposed model can be applied to computer aided design (CAD) of very large-scale integrated circuits (VLSIs) in nano-scale technologies. © 2009 Chin. Phys. Soc. and IOP Publishing Ltd.

Number of references: 13

Main heading: Computer aided design

Controlled terms: Computer circuits - Heating - Integrated circuits - Metallic compounds - MOS devices - Nanostructured materials - Temperature distribution - Thermal conductivity - Thermoanalysis - Thermography (temperature measurement)

Uncontrolled terms: Complementary metal oxide semiconductor process - Global interconnects - Heat diffusion equations - Local interconnects - Multi level interconnects - Nano scale - Reduction of thermal conductivity - Scale integrated circuits - Self-heating - Substrate temperature - Thermal model - Via effect

Classification code: 761 Nanotechnology - 801 Chemistry - 804.1 Organic Compounds - 723.5 Computer Applications - 804.2 Inorganic Compounds - 933.1 Crystalline Solids - 944.6 Temperature Measurements - 931.2 Physical Properties of Gases, Liquids and Solids - 721.3 Computer Circuits - 462.1 Biomedical Equipment, General - 641.1 Thermodynamics - 641.2 Heat Transfer - 461.1 Biomedical Engineering - 642.1 Process Heating - 703.1 Electric Networks - 714.2 Semiconductor Devices and Integrated Circuits - 643.1 Space Heating

DOI: 10.1088/1674-1056/18/11/063

Database: Compendex