Error (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("bError (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("begin" is a reserved keyword),or "constant",or "file",or

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Error(10500):VHDLsyntaxerroratbiaojue.vhd(16)neartext"begin";expectinganidentifier("bError(10500):VH

Error (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("bError (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("begin" is a reserved keyword),or "constant",or "file",or
Error (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("b
Error (10500):VHDL syntax error at biaojue.vhd(16) near text "begin"; expecting an identifier ("begin" is a reserved keyword),or "constant",or "file",or "signal",or "variable"
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity biaojue is\x05
port (
xin:in std_logic_vector ( 6 downto 0 );
sel2:out std_logic;
);
end biaojue ;
architecture bev of biaojue is
begin
process ( xin );
variable j:integer :=0
begin
j:=0;
for i in 0 to 6 loop
if xin(i)='1' then
j:=j+1;
end if ;
end loop;
if j>3 then
sel2