VHDL 求大神帮我调试library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------------------------------------------------------------------------------------entity lock

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VHDL求大神帮我调试libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsi

VHDL 求大神帮我调试library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------------------------------------------------------------------------------------entity lock
VHDL 求大神帮我调试
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------------------------------------------------------------------------------------
entity lock is
port( Clk :in std_logic; --时钟信号
Rst :in std_logic; --复位信号
Kr :in std_logic_vector(3 downto 0); --键盘行
Kc :buffer std_logic_vector(3 downto 0); --键盘列
SPK :out std_logic; --扬声器输出
KEY_State :out std_logic; --按键指示
Door :buffer std_logic; --门状态
Display :out std_logic_vector(7 downto 0); --七段码管显示
SEG_SEL :buffer std_logic_vector(2 downto 0); --七段码管片选
enter_2,enter_1 :in std_logic; --设密码确认及输入密码确认
datain :in std_logic_vector(3 downto 0)); --密码数据输入
end lock;
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architecture behave of lock is
signal keyr,keyc :std_logic_vector(3 downto 0);
signal kcount :std_logic_vector(2 downto 0);
signal kflag1,kflag2 :std_logic;
signal buff1,buff2,buff3,buff4,buff5,buff6 :integer range 0 to 15;
signal push_num :integer range 0 to 15; --按键次数
signal Disp_Temp :integer range 0 to 15;
signal Disp_Decode :std_logic_vector(7 downto 0);
signal SEC1,SEC10 :integer range 0 to 9;
signal Clk_Count1 :std_logic_vector(3 downto 0); --1KHz时钟分频计数器
signal Clk_Count2 :std_logic_vector(9 downto 0); --2Hz时钟分频计数器
signal Clk1KHz :std_logic;
signal Clk2Hz :std_logic;
signal Clk1Hz :std_logic;
signal clk_1k :std_logic;
signal Error_Num :integer range 0 to 3;
signal Error_Flag :std_logic;
signal Error_Count :std_logic_vector(2 downto 0);
signal Music_Count :std_logic_vector(2 downto 0);
signal ram:std_logic_vector(3 downto 0);
signal judge:std_logic;
signal turn_on,turn_off:std_logic;
begin
process(Clk)
begin
if(Clk'event and Clk='1') then
if(Clk_Count1