英语翻译1 系统设计在待设计的接收机中,接收信号为70MHz中频、10MHz带宽的OFDM信号.不同于传统接收机结构对70MHz中频信号模拟下变频然后进行采样的做法,在PDR结构的接收机中,直接在中频上进

英语翻译1 系统设计在待设计的接收机中,接收信号为70MHz中频、10MHz带宽的OFDM信号.不同于传统接收机结构对70MHz中频信号模拟下变频然后进行采样的做法,在PDR结构的接收机中,直接在中频上进
英语翻译
1 系统设计
在待设计的接收机中,接收信号为70MHz中频、10MHz带宽的OFDM信号.不同于传统接收机结构对70MHz中频信号模拟下变频然后进行采样的做法,在PDR结构的接收机中,直接在中频上进行采样,采样频率为80MHz,然后对采样后的信号进行数字下变频和4倍的抽取滤波,得到速率为20M Baud的基带信号,送至DSP、FPGA部分解调.降速率的目的在于减轻DSP及FPGA的运算负荷.电路结构如图1所示.
2 GCl012B及其配置
自Graychip公司(现已被TI收购)推出了世界上第一款数字下变频ASIC以来,目前许多公司都开发了数字下变频芯片,比较著名的还有Harris(1999年已更名为Intersil)、ADI和Stanford Telecom等.
电路中使用的数字下变频器是Graychip公司的GCl012B.GCl012B为3．3V电源供电CMOS器件,输入信号最高采样率100MHz,带宽50MHz.GCl012B不兼容5V电平,不可将5V电乎的信号直接接到其任何管脚上,否则将损坏器件.内部模块包括数控振荡器、数字混频器、可变速率抽取低通滤波器、可调增益放大器、数据格式选择模块等.通过微处理器接口对内部寄存器进行配置可以改变芯片的工作状态.其结构如图2所示.
该芯片为120管脚QFP封装,在3．3V电源供电、70MHz信号输入的情况下功耗约为900mW.其动态范围达75dB以上,频率分辨率0．1Hz,增益调节步进为0．03dB.芯片的输出模式有实数、复数两种选择.设置为实数模式时,仅在I端口输出数据；设置为复数模式时,输出I、Q两路正交数据.输人数据宽度为12位,输出数据宽度为16位.
GCl012B的工作状态由内部寄存器中的控制字确定.系统上电时,可以使用单片机通过与GCl012B的微处理器接口配置.调谐频率／由28bit的FREQ按(1)式确定,其中fs为输入信号的采样频率.
在本系统中,采样频率为80MHz,调谐频率值为10MHz,所以FREQ：(2000000)HEX.GCl012B按照SS#信号同步数据与状态字,变频至基带,进行4倍抽取并翻转频谱,以复数形式输出I、Q两路数据.

英语翻译1 系统设计在待设计的接收机中,接收信号为70MHz中频、10MHz带宽的OFDM信号.不同于传统接收机结构对70MHz中频信号模拟下变频然后进行采样的做法,在PDR结构的接收机中,直接在中频上进
1,System Design
In the question of the receiver design,signal reception for the 70 MHz IF,10 MHz bandwidth OFDM signal.Unlike traditional receiver structure on the 70 MHz IF frequency analog signals then proceed to the practice of sampling in the structure of the receiver PDR,the direct IF sampling,the sampling frequency is 80 MHz,then sampling the signal and digital downconversion four times the filter taken by M Baud rate of 20 baseband signal sent to the DSP,FPGA part demodulator.Drop aimed at reducing the rate of DSP and FPGA computing load.Circuit structure as shown in Figure 1.
2 GCl012B and configuration
Since Graychip company (now acquired by TI) introduced the world's first digital downconversion ASIC,which many companies have developed a Digital Downconversion chips,there are relatively well-known Harris (1999,it has changed its name to Intersil),ADI and Stanford Telecom,etc..
The figures used in the circuit of the inverter is Graychip GCl012B.GCl012B 3.3 V power supply CMOS devices,the maximum input signal sampling rate of 100 MHz,50 MHz bandwidth.GCl012B not compatible with 5 V level,will not be allowed between 5 V,the signal directly from any of its pins,otherwise,they will damage devices.NC modules including internal oscillator,digital mixer,variable rate from low-pass filter,variable gain amplifier,data formats,such as choice of modules.Microprocessor interface through the internal registers to configure the chip can be changed working conditions.Its structure as shown in Figure 2.
The chip is 120-pin QFP packages,in the 3.3 V power supply,70 MHz signal input of about 900 mW of power.The dynamic range of over 75 dB,0.1 Hz frequency resolution,gain adjustment step is 0.03 dB.Chip output modes are real,complex two options.Set to real mode,I only port in the output data set to multiple mode,the output I,Q quadrature data from two directions.Input data width is 12,the output data width is 16.
GCl012B work in the state of internal registers from the controlled vocabulary identified.Power system,the microcontroller can be used with GCl012B microprocessor interface configurations.Tuning frequency / from 28-bit FREQ by (1) shall be determined,which fs for the input signal sampling frequency.
In this system,the sampling frequency is 80 MHz,tuning frequency of 10 MHz,so FREQ:(2000000) HEX.GCl012B SS # signal synchronization in accordance with the data and status word to the baseband frequency,and overturned four times from the spectrum to the plural form of output I and Q data from two directions.